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LTC4150 1 4150f applicatio s u features typical applicatio u descriptio u current sense voltage (mv) ?0 ?5 0 25 50 error (% full scale) 4150 ta01b 0.5 0.4 0.3 0.2 0.1 0.5 0.4 0.3 0.2 0.1 0 the ltc ? 4150 measures battery depletion and charging in handheld pc and portable product applications. the de- vice monitors current through an external sense resistor between the batterys positive terminal and the batterys load or charger. a voltage-to-frequency converter trans- forms the current sense voltage into a series of output pulses at the interrupt pin. these pulses correspond to a fixed quantity of charge flowing into or out of the battery. the part also indicates charge polarity as the battery is depleted or charged. the LTC4150 is intended for 1-cell or 2-cell li-ion and 3-cell to 6-cell nicd or nimh applications. n battery chargers n palmtop computers and pdas n cellular telephones and wireless modems , ltc and lt are registered trademarks of linear technology corporation. c f c f + int 4.7 f clr chg dischg r l r sense pol shdn 4.7 f charger load sense sense + gnd LTC4150 p 4150 ta01a v dd + r l integral nonlinearity, % of full scale n indicates charge quantity and polarity n 50mv sense voltage range n precision timer capacitor or crystal not required n 2.7v to 8.5v operation n high side sense n 32.55hz/v charge count frequency n 1.5 m a shutdown current n 10-pin msop package coulomb counter/ battery gas gauge
LTC4150 2 4150f supply voltage (v dd ) ...................................C 0.3v to 9v input voltage range digital inputs (clr, shdn) ....... C 0.3v to (v dd + 0.3) sense C , sense + , c f C , c f + ........ C 0.3v to (v dd + 0.3) output voltage range digital outputs (int, pol) .......................C 0.3v to 9v operating temperature range ..................... 0 c to 70 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number ms part marking t jmax = 125 c, q ja = 160 c/w consult ltc marketing for parts specified with wider operating temperature ranges. ltqw LTC4150cms absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 2.7v and 8.5v unless otherwise noted. 1 2 3 4 5 sense + sense c f + c f shdn 10 9 8 7 6 int clr v dd gnd pol top view ms package 10-lead plastic msop symbol parameter conditions min typ max units v il digital input low voltage, clr, shdn l 0.7 v v ih digital input high voltage, clr, shdn l 1.9 v v ol digital output low voltage, int, pol i ol = 1.6ma, v dd = 2.7v l 0.5 v i leak digital output leakage current, int, pol v int = v pol = 8.5v l 0.01 1 m a v os differential offset voltage, (note 4) v dd = 4.0v 100 m v l 150 m v v dd = 8.0v 100 m v l 150 m v v dd = 2.7v to 8.5v 150 m v l 200 m v v sense(cm) sense voltage common mode input range l v dd C 0.06 v dd + 0.06 v v sense sense voltage differential input range sense + C sense C l C 0.05 0.05 v r idr average differential input resistance, v dd = 4.1v, (note 3) 155 270 390 k w across sense + and sense C v uvlo undervoltage lockout threshold v dd rising l 2.5 2.7 v power supply current i dd supply current, operating v dd = 8.5v l 115 140 m a v dd = 2.7v l 80 100 m a i dd(sd) supply current, shutdown v dd = 8.5v l 10 m a v dd = 2.7v l 1.5 m a ac characteristics g vf voltage to frequency gain v sense = 50mv to C 50mv, 32.0 32.55 33.1 hz/v 2.7v v dd 8.5v l 31.8 33.3 hz/v d g vf (v dd ) gain variation with supply 2.7v v dd 8.5v 0 0.5 %/v d g vf (temp) gain variation with temperature (note 2) l C 0.03 0.03 %/ oc inl integral nonlinearity C 0.4 0.4 % l C 0.5 0.5 full scale t clr clr pulse width to reset int, figure 2, v dd = 4.1v 20 m s int and clr not connected t int int low time, int connected to clr figure 3, c l = 15pf l 1 m s note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: guaranteed by design and not tested in production. note 3: measured at least 20ms after power on. note 4: tested in feedback loop to sense + and sense C .
LTC4150 3 4150f (specifications are at t a = 25 c, unless otherwise noted.) v dd (v) 23468 579 g vf error (% of typical) 4150 g01 +1.00 ?.00 ?.75 ?.50 ?.25 0 +0.25 +0.50 +0.75 v sense = 25mv v sense = 50mv v dd (v) 23468 579 v ol (mv) 4150 g05 400 0 50 100 150 200 250 300 350 pol pin i ol = 1.6ma int pin typical perfor a ce characteristics uw voltage to frequency gain vs supply voltage voltage to frequency gain vs temperature operating i dd vs v dd temperature ( c) -50 -25 0 50 100 25 75 125 g vf error (% of typical) 4150 g02 +1.00 ?.00 ?.75 ?.50 ?.25 0 +0.25 +0.50 +0.75 v sense = 50mv v dd = 2.7v v dd = 8.5v v dd (v) 234 68 57910 i dd ( a) 4150 g03 140 120 100 80 60 v dd (v) 234 68 57910 i dd ( a) 4150 g04 6 5 4 3 2 1 0 shutdown i dd vs v dd digital output low voltage vs v dd undervoltage lockout threshold vs temperature uvlo (v) 4150 g06 2.60 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 rising edge temperature ( c) -50 -25 0 50 100 25 75 125
LTC4150 4 4150f pi fu ctio s uuu sense + (pin 1): positive sense input. this is the noninverting current sense input. connect sense + to the load and charger side of the sense resistor. full-scale current sense input is 50mv. sense + must be within 60mv of v dd for proper operation. sense C (pin 2): negative sense input. this is the inverting current sense input. connect sense C to the positive battery terminal side of the sense resistor. full-scale current sense input is 50mv. sense C must be within 60mv of v dd for proper operation. c f + (pin 3): filter capacitor positive input. a capacitor connected between c f + and c f C filters and averages noise and fast battery current variations. a 4.7 m f value is recom- mended. if filtering is not desired, leave c f + and c f C unconnected. c f C (pin 4): filter capacitor negative input. a capacitor connected between c f + and c f C filters and averages noise and fast battery current variations. a 4.7 m f value is recom- mended. if filtering is not desired, leave c f + and c f C unconnected. shdn (pin 5): shutdown digital input. when asserted low, shdn forces the LTC4150 into its low current con- sumption power-down mode and resets the part. in appli- cations with logic supply v cc > v dd , a resistive divider must be used between shdn and the logic which drives it. see the applications information section. pol (pin 6): battery current polarity open-drain output. pol indicates the most recent battery current polarity when int is high. a low state indicates the current is flowing out of the battery while high impedance means the current is going into the battery. pol latches its state when int is asserted low. pol is an open-drain output and can be pulled up to any logic supply up to 9v. in shutdown, pol is high impedance. gnd (pin 7): ground. connect directly to the negative battery terminal. v dd (pin 8): positive power supply. connect to the load and charger side of the sense resistor. sense + also connects to v dd . v dd operating range is 2.7v to 8.5v. bypass v dd with 4.7 m f capacitor. clr (pin 9): clear interrupt digital input. when asserted low for more than 20 m s, clr resets int high. charge counting is unaffected . int may be directly connected to clr. in this case the LTC4150 will capture each assertion of int and wait at least 1 m s before resetting it. this ensures that int pulses low for at least 1 m s but gives automatic int reset. in applications with a logic supply v cc > v dd , a resistive divider must be used between int and clr. see the applications information section. int (pin 10): charge count interrupt open-drain output. int latches low every 1/(v sense ? g vf ) seconds and is reset by a low pulse at clr. int is an open-drain output and can be pulled up to any logic supply of up to 9v. in shutdown int is high impedance.
LTC4150 5 4150f ti i g diagra s w u w t clr 4150 f02 50% clr int 50% t int 4150 f03 50% int 50% figure 2. clr pulse width to reset int, clr and int not connected figure 3. int minimum pulse width, clr and int connected + + + amplifier c f + c f sense + v dd r sense i bat c f sense 2k 2k 200k 200k 100pf 200k s2 s1 s3 shdn control logic polarity detection oflow/ uflow refhi 1.7v reflo 0.95v clr pol discharge charge int gnd load charger counter up/dn r sq 4150 f01 figure 1. block diagram block diagra w
LTC4150 6 4150f operatio u charge is the time integral of current. the LTC4150 measures battery current by monitoring the voltage devel- oped across a sense resistor and then integrates this information in several stages to infer charge. the block diagram shows the stages described below. as each unit of charge passes into or out of the battery, the LTC4150 int pin interrupts an external microcontroller and the pol pin reports the polarity of the charge unit. the external microcontroller then resets int with the clr input in preparation for the next interrupt issued by the LTC4150. the value of each charge unit is determined by the sense resistor value and the sense voltage to interupt frequency gain g vf of the LTC4150. power-on and start-up initialization when power is first applied to the LTC4150, all internal circuitry is reset. after an initialization interval, the LTC4150 begins counting charge. this interval depends on v dd and the voltage across the sense resistor but will be at least 5ms. it may take an additional 80ms for the LTC4150 to accurately track the sense voltage. an internal undervolt- age lockout circuit monitors v dd and resets all circuitry when v dd falls below 2.5v. asserting shdn low also resets the LTC4150s internal circuitry and reduces the supply current to 1.5 m a. in this condition, pol and int outputs are high impedance. the LTC4150 resumes counting after another initialization interval. shutdown minimizes battery drain when both the charger and load are off. charge counting first, the current measurement is filtered by capacitor c f connected across pins c f + and c f C . this averages fast changes in current arising from ripple, noise and spikes in the load or charging current. second, the filters output is applied to an integrator with the amplifier and 100pf capacitor at its core. when the integrator output ramps to refhi or reflo levels, switches s1 and s2 reverse the ramp direction. by observing the condition of s1 and s2 and the ramp direction, polarity is determined. the integrating interval is trimmed to 600 m s at 50mv full-scale sense voltage. third, a counter is incremented or decremented every time the integrator changes ramp direction. the counter effec- tively increases integration time by a factor of 1024, greatly reducing microcontroller overhead required to service interrupts from the LTC4150. at each counter under or overflow, the int output latches low, flagging a microcontroller. simultaneously, the pol output is latched to indicate the polarity of the observed charge. with this information, the microcontroller can total the charge over long periods of time, developing an accurate estimate of the batterys condition. once the interrupt is recognized, the microcontroller resets int with a low going pulse on clr and awaits the next interrupt. alternatively, int can drive clr.
LTC4150 7 4150f sense voltage input and filters since the overall integration time is set by internally trimming the LTC4150, no external timing capacitor or trimming is necessary. the only external component that affects the transfer function of interrupts per coulomb of charge is the sense resistor, r sense . the common mode range for the sense + and sense C pins is v dd 60mv, with a maximum differential voltage range of 50mv. sense + is normally tied to v dd , so there is no common mode issue when sense C operates within the 50mv differential limit relative to sense + . choose r sense to provide 50mv drop at maximum charge or discharge current, whichever is greater. calculate r sense from: r mv i sense max = 50 (1) the sense input range is small ( 50mv) to minimize the loss across r sense . to preserve accuracy, use kelvin connections at r sense . the external filter capacitor c f operates against a total on- chip resistance of 4k to form a lowpass filter that averages battery current and improves accuracy in the presence of noise, spikes and ripple. 4.7 m f is recommended for gen- eral applications but can be extended to higher values as long as the capacitors leakage is low. a 10na leakage is roughly equivalent to the input offset error of the integra- tor. ceramic capacitors are suitable for this use. switching regulators are a particular concern because they generate high levels of current ripple which may flow through the battery. the v dd and sense + connection to the charger and load should be bypassed by at least 4.7 m f at the LTC4150 if a switching regulator is present. the LTC4150 maintains high accuracy even when burst mode ? switching regulators are used. burst pulse on levels must be within the specified differential input volt- age range of 50mv as measured at c f + and c f C . to retain accurate charge information, the LTC4150 must remain enabled during burst mode operation. if the LTC4150 shuts down or v dd drops below 2.5v, the part resets and charge information is lost. applicatio s i for atio wu u u coulomb counting the LTC4150s transfer function is quantified as a voltage to frequency gain g vf , where output frequency is the number of interrupts per second and input voltage is the differential drive v sense across sense + and sense C . the number of interrupts per second will be: f = g vf ? ? v sense ? (2) where v sense = i battery ? r sense (3) therefore, f = g vf ? ? i battery ? r sense ? (4) since i ? t = q, coulombs of battery charge per int pulse can be derived from equation 4: one int gr coulombs vf sense = 1 (5) battery capacity is most often expressed in ampere-hours. 1ah = 3600 coulombs (6) combining equations 5 and 6: one int gr vf sense = 1 3600 [ah] (7) or 1ah = 3600 ? g vf ? r sense interrupts (8) the charge measurement may be further scaled within the microcontroller. however, the number of interrupts, cou- lombs or ah all represent battery charge. the LTC4150s transfer function is set only by the value of the sense resistor and the gain g vf . once r sense is selected using equation 1, the charge per interrupt can be determined from equation 5 or 7. note that r sense is not chosen to set the relationship between ampere-hours of battery charge and number of interrupts issued by the LTC4150. rather, r sense is chosen to keep the maximum sense voltage equal to or less than the LTC4150s 50mv full-scale sense input. burst mode is registered trademark of linear technology corporation.
LTC4150 8 4150f int, pol and clr int asserts low each time the LTC4150 measures a unit of charge. at the same time, pol is latched to indicate the polarity of the charge unit. the integrator and counter continue running, so the microcontroller must service and clear the interrupt before another unit of charge accumu- lates. otherwise, one measurement will be lost. the time available between interrupts is the reciprocal of equation 2: time per int assertion gv vf sense = 1 ?? (9) at 50mv full scale, the minimum time available is 596ms. to be conservative and accommodate for small, unex- pected excursions above the 50mv sense voltage limit, the microcontroller should process the interrupt and polarity information and clear int within 500ms. toggling clr low for at least 20 m s resets int high and unlatches pol. since the LTC4150s integrator and counter operate independently of the int and pol latches, no charge information is lost during the latched period or while clr is low. charge/discharge information continues to accumulate during those intervals and accuracy is unaffected. once cleared, int idles in a high state and pol indicates real-time polarity of the battery current. pol high indi- cates charge flowing into the battery and low indicates charge flowing out. indication of a polarity change re- quires at least: t gv pol vf sense = 2 1024 ?? (10) where v sense is the smallest sense voltage magnitude before and after the polarity change. open-drain outputs pol and int can sink i ol = 1.6ma at v ol = 0.5v. the minimum pull-up resistance for these pins should be: r l > (v cc C 0.5) / 1.6ma (11) where v cc is the logic supply voltage. because speed isnt an issue, pull-up resistors of 10k or higher are adequate. applicatio s i for atio wu u u interfacing to int, pol, clr and shdn the LTC4150 operates directly from the battery, while in most cases the microcontroller supply comes from some separate, regulated source. this poses no problem for int and pol because they are open-drain outputs and can be pulled up to any voltage 9v or less, regardless of the voltage applied to the LTC4150s v dd . clr and shdn inputs require special attention. to drive them, the microcontroller or external logic must generate a minimum logic high level of 1.9v. the maximum input level for these pins is v dd + 0.3v. if the microcontrollers supply is more than this, resistive dividers must be used on clr and shdn. the schematic in figure 6 shows an application with int driving clr and microcontroller v cc > v dd . the resistive dividers on clr and shdn keep the voltages at these pins within the LTC4150s v dd range. choose r2 and r1 so that: (r1 + r2) 3 50r l (12) 19 1 12 .() v r rr v v minimum cc dd + (13) equation 13 also applies to the selection of r3 and r4. the minimum v dd is the lowest supply to the LTC4150 when the battery powering it is at its lowest discharged voltage. when the battery is removed in any application, the clr and shdn inputs are unpredictable. int and pol outputs may be erratic and should be ignored until after the battery is replaced. if desired, the simple logic of figure 4 may be used to derive separate charge and discharge pulse trains from int and pol. figure 4. unravelling polarity separate charge and discharge outputs int charge discharge clr pol LTC4150 4150 f04
LTC4150 9 4150f figure 5. application with int direct drive of clr and separate microprocessor supply v cc v dd applicatio s i for atio wu u u automatic charge count interrupt and clear in applications where a clr pulse is unavailable, its easy to make the LTC4150 run autonomously, as shown in figures 5 and 6. if the microcontroller v cc is less than or equal to the battery v dd , int may be directly connected to clr, as in figure 5. the only requirement is that the microcontroller should be able to provide a high logic level of 1.9v to shdn. if the microcontroller v cc is greater than the battery v dd , use figure 6. the resistor dividers on clr and shdn keep the voltages at these pins within the LTC4150s v dd range. choose an r l value using equation 11 and r1-r4 values using equation 13. in either applica- tion, the LTC4150 will capture the first assertion of int and wait at least 1 m s before resetting it. this insures that int pulses low for at least 1 m s but gives automatic int reset. int sense + sense shdn clr pol LTC4150 p c2 4.7 f r l 10 9 8 7 6 1 2 5 4150 f05 v dd gnd r l processor v cc power-down switch c l 47 f load + c f + c f 3 4 c f 4.7 f 2.7v to 8.5v battery r sense int sense + sense shdn shutdown r4 r3 clr pol LTC4150 p c2 4.7 f r l 10 9 8 7 6 1 2 5 4150 f06 v dd gnd r l processor v cc power-down switch c l 47 f load + c f + c f 3 4 c f 4.7 f battery v battery < v cc r sense r2 r1 figure 6. application with int driving clr and separate microprocessor supply v cc > v dd
LTC4150 10 4150f figure 8 shows a typical application designed for a single cell lithium-ion battery and 500ma maximum load current. use equation 1 to calculate r sense = 0.05v / 0.5a = 0.1 w . with r sense = 0.1 w , equation 7 shows that each interrupt corresponds to 0.085mah. equation 14, derived from equation 2, gives the number of int assertions for average battery current, i batt , over a time, t, in seconds: int assertions = g vf ? i batt ? r sense ? t (14) loading the battery so that 51.5ma is drawn from it over 600 seconds results in 100 int assertions. for an 800mah battery, this is (51.5ma ? 1/6h) / 800mah = 11% of the batterys capacity. pc board layout suggestions keep all traces as short as possible to minimize noise and inaccuracy. the supply bypass capacitor c2 should be placed close to the LTC4150. the 4.7 m f filter capacitor c f should be placed close the c f + and c f C pins and should be a low leakage, unpolarized type. use a 4-wire kelvin sense connection for the sense resistor, locating it close to the LTC4150 with short sense traces to the sense + and sense C pins and longer force lines to the battery pack and powered load, see figure 7. applicatio s i for atio wu u u 4150 f07 pin 1 to battery to charger LTC4150 r sense figure 7. kelvin connection on sense resistor typical applicatio s u with a microcontroller supply = 5v, equation 11 gives r l > 2.875k. the nearest standard value is 3k. from equation 12, r l = 3k gives r1 + r2 equal to 150.5k. a single cell lithium-ion battery can discharge as low as 2.7v. from equation 13, select r1 = 75k; the nearest standard value for r2 is 76.8k. also from equation 13, we choose r3 = 75k and r4 = 76.8k. int sense + sense shdn shutdown r4 76.8k r3 75k clr pol LTC4150 p c2 4.7 f r l 3k 10 9 8 7 6 1 2 5 4150 f08 v dd gnd r l 3k 5.0v power-down switch c l 47 f load c f + c f 3 4 c f 4.7 f single-cell li-ion 3.0v ~ 4.2v r sense 0.1 r2 76.8k r1 75k + figure 8. typical application, single cell lithium-ion battery
LTC4150 11 4150f package descriptio u msop (ms) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC4150 12 4150f part number description comments ltc1732 lithium-ion linear battery charger controller simple charger uses external fet, features preset voltages, c/10 charger detection and programmable timer, input power good indication ltc1733 monolithic lithium-ion linear battery charger standalone charger with programmable timer, up to 1.5a charge current ltc1734 lithium-ion linear battery charger in thinsot tm simple thinsot charger, no blocking diode, no sense resistor needed ltc1734l lithium-ion linear battery charger in thinsot low current version of ltc1734 ltc1998 lithium-ion low battery detector 1% accurate 2.5 m a quiescent current, sot-23 ltc4006 small, high efficiency, fixed voltage, constant-current/constant voltage switching regulator with termination lithium-ion battery charger timer, ac adapter current limit and thermistor sensor in a small 16-pin package ltc4050 lithium-ion linear battery charger controller simple charger uses external fet, features preset voltages, c/10 charger detection and programmable timer, input power good indication, thermistor interface ltc4052 monolithic lithium-ion battery pulse charger no blocking diode or external power fet required, safety current limit ltc4053 usb compatible monolithic lithium-ion battery charger standalone charger with programmable timer, up to 1.25a charge curr ent ltc4054 800ma standalone linear lithium-ion battery charger no external mosfet, sense resistor or blocking diode required, charge with thermal regulation in thinsot current monitor for gas gauging, c/10 charge termination ltc4410 usb power manager for simultaneous operation of usb peripheral and battery charging from usb port, keeps current drawn from usb port constant, keeps battery fresh, use with the ltc4053, ltc1733, ltc4054 ltc4412 powerpath? controller in thinsot more efficient diode oring, automatic switching between dc sources, simplified load sharing, 3v v in 28v thinsot and powerpath are trademarks of linear technology corporation. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2003 lt/tp 0703 1k ? printed in usa related parts typical applicatio s u 1.1 1.2 100m sense resistance = 0.0852 i max = 588ma 10,000 pulses = 1ah + int sense + sense clr 4150 f09 LTC4150 cd40110b cd40110b cd40110b cd40110b cd40110b load charger figure 9. ampere-hour gauge

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